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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v<br>
H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v<br>
H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v<br>
H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v<br>
H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v<br>
H:\Gowin\Gowin_V1.9.9Beta-5\IDE\data\ipcores\gw_jtag.v<br>
H:\nestang\nestang-master-25k\impl\gao\gw_gao_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Oct 27 15:38:08 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>gw_gao</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.926s, Peak memory usage = 38.566MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 38.566MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 38.566MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.566MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 38.566MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 50.891MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 50.891MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 50.891MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 50.891MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>38</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>38</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>37</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>479</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>442</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>513</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>105</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>372</td>
</tr>
<tr>
<td class="label"><b>MUX </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMUX16</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>10</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPX9B</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Black Box </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspGW_JTAG</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>535(525 LUT, 10 ALU) / 23040</td>
<td>3%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>479 / 23280</td>
<td>3%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23280</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>479 / 23280</td>
<td>3%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>3 / 56</td>
<td>6%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>sys_clk_ibuf/I </td>
</tr>
<tr>
<td>u_icon_top/n19_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>u_icon_top/n19_s2/O </td>
</tr>
<tr>
<td>u_la0_top/n15_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>u_la0_top/n15_s2/O </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>100.0(MHz)</td>
<td>272.4(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>u_icon_top/n19_6</td>
<td>100.0(MHz)</td>
<td>627.0(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>u_la0_top/n15_6</td>
<td>100.0(MHz)</td>
<td>1577.9(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.329</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.230</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.559</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/I0</td>
</tr>
<tr>
<td>2.680</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/F</td>
</tr>
<tr>
<td>2.867</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/I2</td>
</tr>
<tr>
<td>3.329</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>11</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/F</td>
</tr>
<tr>
<td>3.516</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0</td>
</tr>
<tr>
<td>4.043</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F</td>
</tr>
<tr>
<td>4.230</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>10.559</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.040, 60.714%; route: 0.938, 27.902%; tC2Q: 0.382, 11.384%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.641</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.165</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.806</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/I0</td>
</tr>
<tr>
<td>2.680</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/F</td>
</tr>
<tr>
<td>2.867</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/I2</td>
</tr>
<tr>
<td>3.329</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>11</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/F</td>
</tr>
<tr>
<td>3.516</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n318_s3/I2</td>
</tr>
<tr>
<td>3.977</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n318_s3/F</td>
</tr>
<tr>
<td>4.165</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK</td>
</tr>
<tr>
<td>10.806</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.975, 59.940%; route: 0.938, 28.452%; tC2Q: 0.382, 11.608%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.641</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.165</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.806</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/I0</td>
</tr>
<tr>
<td>2.680</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/F</td>
</tr>
<tr>
<td>2.867</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/I2</td>
</tr>
<tr>
<td>3.329</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>11</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/F</td>
</tr>
<tr>
<td>3.516</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n317_s1/I2</td>
</tr>
<tr>
<td>3.977</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n317_s1/F</td>
</tr>
<tr>
<td>4.165</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK</td>
</tr>
<tr>
<td>10.806</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.975, 59.940%; route: 0.938, 28.452%; tC2Q: 0.382, 11.608%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.641</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.165</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.806</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/I0</td>
</tr>
<tr>
<td>2.680</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/F</td>
</tr>
<tr>
<td>2.867</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/I2</td>
</tr>
<tr>
<td>3.329</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>11</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/F</td>
</tr>
<tr>
<td>3.516</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n315_s1/I2</td>
</tr>
<tr>
<td>3.977</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n315_s1/F</td>
</tr>
<tr>
<td>4.165</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK</td>
</tr>
<tr>
<td>10.806</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.975, 59.940%; route: 0.938, 28.452%; tC2Q: 0.382, 11.608%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.641</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.165</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.806</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s11/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/I0</td>
</tr>
<tr>
<td>2.680</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s9/F</td>
</tr>
<tr>
<td>2.867</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/I2</td>
</tr>
<tr>
<td>3.329</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>11</td>
<td>u_la0_top/u_ao_mem_ctrl/n309_s5/F</td>
</tr>
<tr>
<td>3.516</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n314_s1/I2</td>
</tr>
<tr>
<td>3.977</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>4.165</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>180</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK</td>
</tr>
<tr>
<td>10.806</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.975, 59.940%; route: 0.938, 28.452%; tC2Q: 0.382, 11.608%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
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